In recent years, with the realization of downsizing and greater packaging density of semiconductor devices, semiconductor elements such as transistors mounted on the semiconductor device are increasingly miniaturized in size.
In fabrication of the transistor, a distinguishing factor that decides the properties is gate length. In microfabrication that decides the gate length, photolithography and etching are used. In photolithography, a photosensitive resin (photoresist) is applied over a semiconductor substrate 100 such as a silicon wafer, and the substrate is exposed at each of predetermined units such as a chip for sequential patterning. The pattern thus formed is developed to form a resin pattern (resist pattern), and the resin pattern is used as a mask for dry etching, for example. In dry etching, the entire surface of the silicon wafer is processed in plasma to etch the silicon material in the area in which no resin pattern is left. Here, the cross sectional structure is schematically shown in FIGS. 4(a) and 4(b). A gate insulating film 110 formed of a silicon oxide film is formed on the semiconductor substrate 100 such as a silicon wafer, polysilicon or a metal material 120 to be a gate electrode is deposited thereon, and then a resin pattern 130 is formed by lithography process steps (FIG. 4(a)). In this state, the semiconductor substrate 100 is brought into a plasma chamber, and an etchant gas, suited for polysilicon or the metal material 120 that is an etching target material, is used for sequential dry etching (FIG. 4(b)).
Then, typically, the pattern of the gate electrode thus formed is used as a mask to dope an impurity material that provides positive or negative properties (to silicon) in a self-aligned manner, and source/drain regions 140 and 150 are formed.
The distance between the source/drain regions thus formed becomes effective gate length. Therefore, the effective gate length is decided by the pattern accuracy of the gate electrode and by the impurity doping accuracy in fabrication thereof.
At first step, in lithography for use in forming the gate electrode, since the substrate is processed highly accurately in units of chips in the size about a 1 cm×1 cm square, it is ideally finished in accuracy with no variations. However, in reality, because variations are sometimes generated in the resin coating thickness in the center part and in the peripheral part of the silicon wafer, slight variations may be generated. On the other hand, in dry etching, since the semiconductor substrate is batch processed in an etching chamber having a limited volume, certain variations are always generated. For example, this becomes a few percentage of variations among silicon wafers or in the surface of a 300 mm silicon wafer.
The gate length described here distinguishingly decides the performance of the transistor, ideally, it is necessary to form the gate length uniformly throughout the surface of a 300 mm wafer.